1. Field
One or more embodiments described herein relate to integrated circuit devices.
2. Description of the Related Art
Scaling techniques have been proposed for increasing the density of integrated circuit devices. One technique involves the use of a multi-gate transistor. Such a transistor may include a fin- or nanowire-shaped silicon body on a substrate. A gate is then formed on a surface of the silicon body.
Because a multi-gate transistor uses a three-dimensional (3D) channel, scaling may be achieved. In addition, current controlling capability can be improved without increasing a gate length of the multi-gate transistor. Further, a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be effectively suppressed.